IEEE

Design of high-precision FFT based on VHDL and analysis of code coverage

Abstract: This paper uses structured design to implement the floating-FFT by VHDL with ISE5.3 and simulates it by ModelSim. The data pathways in this project are in the form of 32-bit single precision ...
GitHub

Using Xilinx Vivado and VHDL

Git repository for the Introduction to FPGA Programming Using Xilinx Vivado and VHDL (16 hours, 4 CFU) PhD course at University of Torino, Physics Department. Lecture slides are available on the main ...
GitHub

A multi-cycle processor of a cpu designed according to the instruction set (assembly language) of RISC-V using System Verilog HDL.

This project implements a multicycle RISC-V processor using SystemVerilog. It is designed to execute a subset of the RISC-V instruction set architecture (ISA) and demonstrates a step-by-step ...