Debugging today’s advanced systems-on-chip (SoCs) is anything but simple. SoC verification environments require tests spanning billions of cycles (Fig. 1). 1. Many classes of bugs become visible only ...

TOKYO, May 08, 2025 (GLOBE NEWSWIRE) -- Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) today unveiled SiConic Test Engineering (TE), the newest addition to the SiConic ...

What is the Conducted EMI measurement? Using FFT-based measuring receivers for CISPR 32. Combining debugging and pre-compliance modes in test equipment. EMC compliance testing of a manufacturer’s ...

With each turn of Moore's Law, designers at every phase in the development process are challenged with new levels of complexity. Chip designers must not only get the integrated circuit (IC) logic, ...

There appears to be an unwritten law about the time spent in debug-it is a constant. It could be that all gains made by improvements in tools and methodologies are offset by increases in complexity, ...

In increasingly complex SoC designs, many of which contain multiple cores and multiple modes, determining best practices for testing and debugging is a moving target. Jason Andrews, architect at ...

Advantest Corp. has unveiled SiConic Test Engineering (TE), the newest addition to the SiConic family introduced in February 2025. SiConic TE offers test engineers the ability to bring up and validate ...

Made up of software and hardware that targets either board-level or embedded memory applications, the DDR3 protocol debug and validation test suite is said to be the industry’s first DDR3 test tool, ...

The verification component of SystemVerilog has dominated the rapid adoption of the language. The new verification syntax in the language allows for dramatic productivity gains in the verification ...

Modern multithreaded, asynchronous code can be hard to debug. The complexity that comes with message passing and thread management results in bugs that can seem non-determinant, with little or no way ...