EDN

Statistical Static Timing Analysis – A Better Alternative

Traditionally static timing analysis (STA) is used to verify if a CMOS digital design can meet the target speed at various process and interconnect corners. In practice, the worst-case slow or ...
Embedded

Static timing analysis: bridging the gap between simulation and silicon

Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is ...
EDN

Rethinking statistical timing analysis

A year or two ago, it looked like statistical timing analysis might be the next great new thing in IC design. Now it's less clear–and a debate at the recent International Symposium on Physical Design ...
Electronic Design

Interview: Cadence's Anirudh Devgan Talks About Parallel Timing Closure Signoff

System-on-Chip (SoC) developers are creating larger and more complex solutions. Static timing analysis and closure is key to successful solution so timing sign off tools can have a significant impact ...
Electronic Design

Oh, The Pain (Of Timing Closure At 28 nm)

What to do, what to do? Chip complexity continues to grow and design schedules are more aggressive, yet design teams are staying the same size or even being scaled back. Something has to give. A key ...