Semiconductor Engineering

What’s So Different About Interposer Signal Integrity?

To achieve gains in power, performance, area, and cost, 3D-IC architectures are pushing electronics design to new limits. Silicon integration technology and associated devices have undergone an ...
Semiconductor Engineering

The Design Challenges Of Clock Integrity And Clock Jitter

Races, missed next-state values due to long paths, and metastability can result from corrupted clock signals. This post describes the challenges of clock network and clock jitter analysis in more ...
Electronic Design

Signal Integrity Analysis for High Speed Datacom Interfaces

Analyzing high speed datacom interfaces is an important task and ensures signal integrity. One major challenge of this analysis is the connection between the physical interface and the oscilloscope, ...
EDN

Problems and pitfalls with signal integrity at 10 Gbits/sec and beyond

Experienced designers of 10 Gbits/sec (10G) Ethernet, SONET/OTN, Infiniband (QDR/FDR), and Fibre channel (16/8GFC) products are well aware that the maintenance of signal quality is far more difficult ...
Electronic Design

Signal-Integrity Analysis Tool Leads Way To SoC Timing Closure

At process technologies of 0.13 µm and smaller, achieving timing closure for system-on-a-chip (SoC) designs becomes a slippery goal. Ever-tinier interconnects are packed closer together, yielding ...
EDN

Simulation tool checks PCB signal integrity

Keysight’s Electrical Performance Scan (EP-Scan) is a digital simulation tool for hardware engineers and PCB designers that performs rapid signal integrity analysis. EP-Scan provides diagnostics to ...
Nature

Signal Integrity and Eye Diagram Analysis in High-Speed Interconnects

Signal integrity is a critical design consideration in modern electronic systems, particularly those that depend on high-speed interconnects. As data rates climb and interconnect geometries become ...