PCIe 6.0 implementations are expandable and hierarchical with embedded switches or switch chips, allowing one root port to interface with multiple endpoints (such as storage devices, Ethernet cards, ...
Rambus has just announced the availability of its next-gen PCIe 6.0 Interface Subsystem that packs PHY and controller IP, with the latest version of the Compute Express Link (CXL) specification ...
PCI-SIG has just announced that the next-gen PCI Express 7.0 specification is already underway. Technical workgroups are now beginning the development of the PCIe Gen 7.0 spec, set to release in 2025.
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