Electronic Design

64-bit Floating Point Coprocessor Supports IEEE 754 Calculations

The uM-FPU64 floating point coprocessor chip provides support for IEEE 754-compatible, 64-bit floating point and integer calculations, expanded digital I/O, and analog input capabilities as well as ...
EDN

Tutorial: Floating-point arithmetic on FPGAs

[Editor's note: For an intro to fixed-point math, see Fixed-Point DSP and Algorithm Implementation. For a comparison of fixed- and floating-point hardware, see Fixed vs. floating point: a surprisingly ...
EDN

Celoxica adds floating-point toolkit to IP portfolio

SAN FRANCISCO — Celoxica Holdings plc, a developer of C language hardware design entry tools and computer acceleration intellectual property (IP) and hardware, has made available a toolkit for ...
Design-Reuse

Single- and double-precision IEEE-754 floating-point unit

The GRFPU is an IEEE-754 compliant floating-point unit, supporting both single and double precision operands. The pipelined design combines high throu ...
Semiconductor Engineering

AI Chips Must Get The Floating-Point Math Right

Most AI chips and hardware accelerators that power machine learning (ML) and deep learning (DL) applications include floating-point units (FPUs). Algorithms used in neural networks today are often ...
Design-Reuse

How to Reduce FPGA Logic Cell Usage by >x5 for Floating-Point FFTs

Here we provide rational for using Centar’s floating-point IP core for the new Altera Arria 10 and Stratix 10 FPGA platforms. After a short contextual discussion section, a comparison of various FFT ...
Electronic Design

HPC And “Big Data” Apps Tap Floating-Point Number Compression

Floating-point values contain three fields: a sign bit, exponent bits, and significand or mantissa bits. The IEEE-754 floating-point number format defined a common floating-point format that most ...