EDN

SystemVerilog reference verification methodology: RTL

The SoC industry needs a reuse-oriented, coverage-driven verification methodology built on the rich semantic support of a standard language. This is the second in a series of four articles outlining a ...
Design-Reuse

SystemC Verification, Simulation & Emulation of Secure Digital IP

This paper describes the process and tools used in the verification of a family of Secure Digital (SD) IP cores. The verification process described included SystemC verification, RTL simulation and ...
Design-Reuse

Transactions in an OVM SystemVerilog Verification Environment

Modeling a verification environment with transactions encompasses many areas, including test bench design and debug, golden model comparison, functional verification between abstraction levels and ...
Semiconductor Engineering

Cell Library Verification Using Symbolic Simulation

Standard cell libraries have been a mainstay of chip design for many decades since the inception of logic synthesis and composition methodologies. Cell library IP typically contains Verilog models ...
Semiconductor Engineering

Evaluation of LLMs on HDL-Based Communication Protocol Generation (U. of Illinois Urbana, CISPA)

A new technical paper titled “ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols” was published by researchers at University of Illinois Urbana Champaign and CISPA ...
EDN

Mixed-signal SOC verification using analog behavioral models

The era of “Internet everywhere” is creating a spectrum of applicationstargeted toward low-power and mixed-signal design,in segments ranging from health care to automotive tocommunications. Meanwhile, ...
Electronic Design

Formal Methodology Validates Cache-Coherence Protocol

Bugs in RTL code are problematic, but a bug in an architectural specification can be catastrophic. If the bug remains undetected until post-silicon debugging, the design process essentially starts all ...