EDN

A short course on SystemVerilog classes for UVM verification

Learning any language can be difficult when so many words take on different meanings in different contexts. “Why does a farmer produce produce?” These homonyms can be confusing even for native ...
Semiconductor Engineering

Verification As A Flow (Part 3)

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, ...
Design-Reuse

Mentor Graphics Adds Memory Models to Create Industry's First Complete UVM SystemVerilog Verification IP Library

WILSONVILLE, Ore., Feb. 29, 2016 – Mentor Graphics Corporation (NASDAQ: MENT) today announced availability of the first entirely native UVM SystemVerilog memory verification IP library for all ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Electronic Design

SystemVerilog Gains A Foothold In Verification

SystemVerilog marries a number of verification concepts, primarily in the areas of design, assertions, and testbench creation, that were previously embodied in separate and sometimes proprietary ...
Electronic Design

Make the Move from Module-Based Mixed-Signal Verification to UVM

This file type includes high resolution graphics and schematics when applicable. This article discusses techniques used to achieve this transition, including proxy SystemVerilog interface task calls ...
EDN

Hardware-assisted verification, from its dawn to SystemVerilog, UVM, and transactors

My [LR’s] first exposure to hardware emulation happened circa 1995 upon visiting a major processor firm in Austin, Texas. Its lab was jam-packed from floor to ceiling with monstrous hardware emulators ...
Semiconductor Engineering

Verification As A Flow (Part 2)

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, ...
mccormick.northwestern.edu

COMP_ENG 387: Real-Time Digital Systems Design and Verification with FPGAs

This course covers the systematic design of real-time digital systems and verification techniques using field-programmable gate arrays (FPGAs). The course presents a top-down design methodology, where ...